Circuit and method for refreshing memory cells in a DRAM

ABSTRACT

The memory cells of a DRAM are refreshed such that the temporal sequence of the control signals for triggering the information refresh operation for the individual memory cells is set in accordance with the respective maximum retention time for the information in the memory cell.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to an apparatus for controlling an informationrefresh operation in memory cells in a memory module and to acorresponding method in which a periodic sequence of control signals fortriggering the information refresh operation is applied to the memorycells.

In dynamic random access memories (DRAMs), it is necessary for theinformation stored in the memory cells to be periodically refreshed,since the memory cells can retain the information stored in them foronly a limited time. The reason for this is that capacitors are used asmemory cells for DRAMs. These capacitors discharge themselves after aspecific time as a result of unavoidable quiescent currents, so that thestored charges of the capacitors have to be regularly renewed. Thememory cells are therefore recharged at fixedly predetermined timeintervals, so-called refresh cycles. The pulse for recharging, theso-called refresh pulse, can be generated internally within the moduleor else externally. In modern DRAMs, refresh cycles of at least 4096refresh operations per 64 ms (refresh rate 6 k/64 ms) are customary.

The refresh cycle for the DRAM, i.e. the interval between the individualrefresh pulses, must be chosen such that even the memory cell with theshortest retention time, which specifies how long the memory content canbe retained in the associated cell, is refreshed again in good time. Theconventional refresh method in the case of DRAMs therefore has theconsequence that even memory cells with longer retention times arerefreshed again prematurely. This leads to an unnecessarily high currentconsumption in the DRAM and shortens, in particular, the operatingduration of accumulator- or battery-operated computers having suchDRAMs. Since the normal writing and reading operations of the DRAM areinterrupted during the refresh operation, e.g. by the presence of aso-called wait command at the processor which controls the DRAM, theavailability of the DRAM is also reduced by the short refresh cyclesrequired for the memory cells.

The article OHSAWA, T.; KAI, K.; MURAKAMI, K.: Optimizing the DRAMrefresh count for merged DRAM/logic LSIs. IN: International Symposion onLow Power Electronics and Design. Proceedings of the IEEE.ISBN1-58113-059-7, 1998, pp. 82-87, discloses a generic type of an apparatusfor controlling an information refresh operation in memory cells in amemory module and a corresponding generic type of method in which thetemporal sequence of the control signals for triggering the refreshoperation of individual memory cell rows can be individually adapted tothe average retention time of the memory cell row. In this case, it isfurthermore possible for the respective refresh cycles to be configuredas an integer multiple of a predetermined basic period.

SUMMARY OF THE INVENTION

It is accordingly an object of the invention to provide an apparatus forcontrolling an information refresh operation and a method forcontrolling an information refresh operation which overcomes theabove-mentioned disadvantages of the prior art apparatus and methods ofthis general type. In particular, it is an object of the invention toprovide an apparatus for controlling an information refresh operationand a method for controlling an information refresh operation thatenable optimized individual setting of the refresh cycle to therespective retention time of a corresponding memory cell. It is also anobject of the present invention, therefore, to develop dynamic randomaccess memories in such a way that the current consumption is reducedand the access time is increased.

With the foregoing and other objects in view there is provided, inaccordance with the invention, an apparatus for controlling aninformation refresh operation in memory cells of a memory module. Theapparatus includes: a control device for applying a periodic sequence ofcontrol signals to memory cells of a memory module for triggering aninformation refresh operation in individual ones of the memory cells;and a test circuit for determining a maximum retention time ofinformation in individual ones of the memory cells in the memory module.The test circuit is connected to the control device. The control deviceis designed to set a temporal sequence of the control signals fortriggering the information refresh operation in the individual ones ofthe memory cells in a variable manner in accordance with the determinedmaximum retention time of the information in the individual one of thememory cells.

In accordance with an added feature of the invention, the control deviceis designed to combine the memory cells of the memory module into groupsin accordance with the determined maximum retention time of informationin the individual ones of the memory cells. The control device assigns,to each individual one of the groups, a respective predetermined timeperiod for applying the control signals to the individual one of thegroups. The predetermined time period is an integer multiple of apredetermined basic period.

With the foregoing and other objects in view there is provided, inaccordance with the invention, a method for controlling an informationrefresh operation in memory cells in a memory module, that includessteps of: providing a memory module having memory cells; using anupstream test cycle to individually determine a maximum retention timeof information in each of the memory cells; applying to the memorycells, a periodic sequence of control signals for triggering aninformation refresh operation; and setting a temporal sequence of thecontrol signals for triggering the information refresh operation inindividual ones of the memory cells in accordance with the determinedmaximum retention time of the information in the individual ones of thememory cells.

In accordance with an added mode of the invention, the method includessteps of: combining the memory cells in the memory module into groups inaccordance with the determined maximum retention time of the informationin each of the memory cells; assigning, to each individual one of thegroups, a respective predetermined time period for applying the controlsignals to the individual one of the groups; and providing thepredetermined time period as an integer multiple of a predeterminedbasic period.

In accordance with an additional mode of the invention, the methodincludes steps of: during the test cycle, for each one of the memorycells: a) reading in a test datum; b) refreshing the test datum with apredetermined frequency; c) reading out the test datum; and d) comparingthe test datum that was read in with the test datum that was read out todetect whether or not there is an error. If no error was detected instep d), then steps a) to d) are repeated with a progressively decreasedrefresh frequency until an error is detected in step d). If the errorwas detected in step d), then steps a) to d) are repeated with aprogressively increased refresh frequency until an error is not detectedin step d).

In the case of the invention's control of an information refreshoperation in memory cells in a memory module, the temporal sequence ofthe control signals for triggering the information refresh operation forthe individual memory cells is coordinated with the respective maximumretention time of the information in the memory cell.

This design of the refresh driving enables the refresh cycle to beindividually adapted to the retention time of the respective cell to berefreshed, that is to say the maximum retention time of the informationin the memory cell. Therefore, it is also no longer necessary to definethe refresh cycle for the memory module in accordance with the shortestretention time that occurs in the module. The result is that the memorycells with longer retention times are also no longer refreshedunnecessarily prematurely. The reduction of the refresh operations inthe memory cells in the memory module, which is possible as a result ofthe utilization of individual refresh cycles, thus provides for asignificant saving in the current consumption. This is particularlyadvantageous in accumulator- or battery-operated computers, in which thereduced power consumption of the memory modules in the refreshoperations enables the maximum operating duration of the computer to besignificantly prolonged.

According to the invention, the maximum retention time of theinformation in the individual memory cells in the memory module isdetermined by a test sequence, in order then to combine the memory cellsin groups preferably in accordance with the defined retention periodsfor memory contents. In this manner, one can define the individualrefresh periods for the refresh operation of a memory cell group. Thisupstream test sequence makes it possible, in a simple manner, toindividually coordinate the refresh times in memory cells and thus tooptimally adapt the power consumption in the respective memory module.

In accordance with a preferred embodiment, the memory cells in thememory module are combined in groups in accordance with the maximumretention time of the memory content. The individual groups are eachassigned a predetermined time period between the successive controlsignals, which is preferably an integer multiple of a predeterminedbasic period. This configuration of the refresh driving makes itpossible to achieve particularly simple assignments between the memorycells and the refresh cycles individually coordinated therewith. Simplegeneration of these individual refresh periods are made possible inparticular by virtue of the design of the individual refresh timeperiods as an integer multiple of a predetermined basic period.

Other features which are considered as characteristic for the inventionare set forth in the appended claims.

Although the invention is illustrated and described herein as embodiedin a circuit and method for refreshing memory cells in a dram, it isnevertheless not intended to be limited to the details shown, sincevarious modifications and structural changes may be made therein withoutdeparting from the spirit of the invention and within the scope andrange of equivalents of the claims.

The construction and method of operation of the invention, however,together with additional objects and advantages thereof will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block illustration of a dynamic random access memory andan integrated refresh logic unit; and

FIG. 2 shows a block diagram of an embodiment of a refresh logic unit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the figures of the drawing in detail and first,particularly, to FIG. 1 thereof, there is shown a block diagram of aDRAM. Reference symbol 1 specifies a refresh driving logic unitintegrated in the DRAM. Reference symbol 2 specifies a row decoder fordecoding address lines A₀-A₄, reference symbol 3 specifies a datacontroller. Reference symbol 4 specifies a column input/output circuit,reference symbol 5 specifies a column coder for decoding the signals fedvia address lines A₅-A₉, and reference symbol 6 specifies a cell matrix.Reference symbol 7 designates a read/write bus, which, in connectionwith the data present at the data controller 3 performs writing to orreading from the cell matrix 6 via the column read-in/output circuit 4in a manner dependent on a read/write signal R/W and a memory selectsignal CS. In the embodiment illustrated, this cell matrix 6 includes 32rows and 32 columns, which corresponds to a dynamic memory having acapacity of 1 Kbit (1024×1 bits).

The refresh of the memory contents of the cell matrix 6 is performed bythe internal refresh driving logic unit 1. In this case, the drivingtakes place row by row, as is customary. To that end, a signal generator11 in the refresh driving logic unit 1 applies a refresh clock signal toa refresh control circuit 12. The control circuit 12 has a further inputfor an inverted chip select signal {overscore (CS)}. In this case, thecontrol circuit 12 is designed in such a way that a refresh pulse isoutput only when the cell matrix 6 is not being addressed, i.e. when aninverted chip select signal {overscore (CS)} is present. What isachieved by this refresh sequence is that the refresh operation issynchronized with the access to the cell matrix 6 in such a way that therefresh operation is performed only when the cell matrix 6 is not beingaccessed. This prevents the refresh operation from giving rise to a timeloss in the event of access to the cell matrix 6.

If an overlap between an external access to the cell matrix 6 and arefresh cycle cannot be entirely precluded, a priority decoder (notshown) can additionally be used, which then acknowledges an externalaccess to the cell matrix with a wait command, so that first the currentrefresh cycle is concluded and afterward the external access is thenperformed.

Besides this technique—also known as the “hidden refresh” method—ofsynchronization between the refresh operation and the access to thememory cells of the cell matrix, it is also possible, however, to employany other known method for temporally dividing the refresh operation andthe access to the cell matrix. In the case of so-called burst refresh,normal operation is always interrupted for the refresh operation and therefresh cycle is then carried out for all of the memory cells of thecell matrix. What is disturbing in this procedure, however, is that thememory module is fundamentally blocked during the refresh operation. Bycontrast, in the case of so-called cycle stealing, contiguous blockingof the cell matrix is avoided by the refresh operation for the cellmatrix being subdivided into a plurality of refresh steps in which onlyindividual areas are refreshed. External access to the cell matrix isthen again blocked during the individual refresh operations.

In addition to generating the refresh clock signal internally within themodule by the signal generator 11, as an alternative, it can also begenerated outside the module, e.g. by a processor.

In a cell matrix 6 of the kind shown in FIG. 1, a refresh rate of 4 k/64ms is generally customary. This high cycle rate is necessary in order toprevent the information which is stored in the memory cells of the cellmatrix and which is present in the form of capacitor charges from beinglost on account of the unavoidable quiescent currents. In this case, therefresh rate of the cell matrix 6 must be set in such a way that, forall of the memory cells of the cell matrix, the capacitors in the memorycells are refreshed in good time, so that no memory contents are lost.Therefore, the required refresh cycle is conventionally determined bythe shortest so-called retention time occurring in the cell matrix, theretention time specifying how long an individual memory cell can retainthe memory information written to it. The consequence of this is thatthe memory cells of the cell matrix 6 with a longer retention time aregenerally already refreshed again prematurely and, as a result, anunnecessarily high current loading is brought about.

In order to adapt the refresh cycles to the respective retention time ofthe memory cells in the cell matrix 6, the refresh driving logic unit 1is designed in such a way that the temporal sequence of the controlsignals for triggering the information refresh operation is, in eachcase, individually coordinated with the individual memory cells of thecell matrix 6. The refresh frequency is set in accordance with themaximum retention time of the memory information in the respectivememory cell. FIG. 2 shows a possible configuration of the refreshcontrol circuit 12, in which individual refresh frequencies are utilizedfor the individual memory cells in the cell matrix 6.

In the embodiment shown in FIG. 2, the memory cells of the cell matrixare divided by way of example into two groups. In which case, the memorycells of one group are intended to be refreshed twice as often as thoseof the other group. These different refresh cycles can be achieved in asimple manner by means of an AND gate 121 configured in the controlcircuit 12. The AND gate 121 logically combines the refresh signal ofthe signal generator 11 with an address signal A(X), which distinguishesbetween the two module halves, a control signal of a 2-bit counter 122,which is driven by the highest cell address A(H) of the cell matrix 6,and an inverted chip signal {overscore (CS)}.

What is achieved by this configuration, in a simple manner, is that,during the refresh operation, a distinction is made between the twomodule halves with their different refresh frequencies. A refresh iseffected only whenever the additional selection signal A(X) for therespective module half is present at the AND gate 121. In order torefresh one group of the cell matrix twice as often as the other group,first two refresh cycles are carried out for the cell group with thehigh refresh frequency and only then is a refresh cycle carried out forthe cell group with the low refresh frequency. In the embodiment shown,in which the cell matrix 6 is divided in half, the current consumptioncan be reduced by a quarter compared with conventional refresh methods.

As an alternative to the embodiment shown in FIG. 2, however, it ispossible to subdivide the cell matrix 6 into more than two groups withan arbitrary number of frequencies. In this case, it is preferable forthe cells to be combined in such a way that the refresh cycles of thedifferent cell groups are integer multiples of a basic periodpredetermined by the signal generator 11. However, it is also possiblefor autonomous, mutually independent refresh cycles to be predeterminedfor the individual cell matrix groups or for each individual memorycell, by individually adapting the refresh frequency that ispredetermined by the signal generator 11 in the refresh control circuit12 in accordance with a predetermined value for each memory cell groupor memory cell.

In this case, the refresh cycle times for the individual memory cells inthe cell matrix 6 can be determined in an upstream test method. For thispurpose, as shown in FIG. 1, a test circuit 13 is provided in therefresh driving logic unit 1. The test circuit 13 is connected to thesignal generator 11 and to the refresh control circuit 12 and isfurthermore connected to the data bus 7 in order to read data into andout of the cell matrix. With the test circuit 13, it is possible, in atargeted manner, for test data to be read into the individual cells ofthe cell matrix 6, and after a predetermined time, to be read out again.At the same time, the test circuit 13 can be used to predetermine therefresh frequency of the signal generator 11 for the memory cell intowhich the test data were read. The signal generator 11 is, for example,of a voltage-controlled design.

The retention times of the memory cells of the cell matrix 6 aredetermined by the test circuit 13 by reading the test data into apredetermined memory cell of the cell matrix 6 during which a fixedrefresh frequency has been set for the memory cell at the signalgenerator 11. After the test data have been read from the memory cell,it is then determined whether the test data written in corresponds tothe test data read out. If this is the case, the refresh frequency isdecreased by a predetermined frequency step and a renewed test cycle isthen performed. This method is repeated iteratively until an error isdetected during the comparison between the test data read in and thetest data read out. As the refresh frequency for the tested memory cell,the test circuit 13 then returns the value of the preceding test stepfor which test data read in and test data read out still corresponded.

Conversely, if an error is detected in the first test step during thecomparison between test data read in and test data read out, the refreshfrequency is increased in predetermined frequency steps until the testdata written in correspond to the test data read out. The resultingrefresh frequency is then the required minimum refresh frequency for thecorresponding memory cell of the cell matrix 6 which is retained by thetest circuit 13.

Then, by means of an evaluation unit in the test circuit 13, the minimumrefresh cycles ascertained in the test circuit 13 for the individualcells of the cell matrix 6 can, if appropriate, be ordered into groupswith an assigned refresh frequency and these cell groups with theiraddresses and the associated refresh frequency can then be communicatedto the refresh control circuit 12.

Consequently, individual refresh frequencies for the individual memorycells of the memory module can be defined in a simple manner using thetest circuit 13 illustrated.

We claim:
 1. An apparatus for controlling an information refreshoperation in memory cells of a memory module, comprising: a controldevice for applying a periodic sequence of control signals to memorycells of a memory module for triggering an information refresh operationin individual ones of the memory cells; and a test circuit fordetermining a maximum retention time of information in individual onesof the memory cells in the memory module, said test circuit connected tosaid control device; said control device constructed to set a temporalsequence of the control signals for triggering the information refreshoperation in the individual ones of the memory cells in a variablemanner in accordance with the determined maximum retention time of theinformation in the individual one of the memory cells.
 2. An apparatusfor controlling an information refresh operation in memory cells of amemory module, comprising: a control device for applying a periodicsequence of control signals to memory cells of a memory module fortriggering an information refresh operation in individual ones of thememory cells; and a test circuit for determining a maximum retentiontime of information in individual ones of the memory cells in the memorymodule, said test circuit connected to said control device; said controldevice constructed to set a temporal sequence of the control signals fortriggering the information refresh operation in the individual ones ofthe memory cells in a variable manner in accordance with the determinedmaximum retention time of the information in the individual one of thememory cells; said control device constructed to combine the memorycells of the memory module into groups in accordance with the determinedmaximum retention time of information in the individual ones of thememory cells; said control device assigning, to each individual one ofthe groups, a respective predetermined time period for applying thecontrol signals to the individual one of the groups, the predeterminedtime period being an integer multiple of a predetermined basic period.3. A method for controlling an information refresh operation in memorycells in a memory module, which comprises: providing a memory modulehaving memory cells; using an upstream test cycle to individuallydetermine a maximum retention time of information in each of the memorycells; applying to the memory cells, a periodic sequence of controlsignals for triggering an information refresh operation; and setting atemporal sequence of the control signals for triggering the informationrefresh operation in individual ones of the memory cells in accordancewith the determined maximum retention time of the information in theindividual ones of the memory cells.
 4. The method according to claim 3,which comprises: combining the memory cells in the memory module intogroups in accordance with the determined maximum retention time of theinformation in each of the memory cells; assigning, to each individualone of the groups, a respective predetermined time period for applyingthe control signals to the individual one of the groups; and providingthe predetermined time period as an integer multiple of a predeterminedbasic period.
 5. The method according to claim 4, which comprises,during the test cycle, for each one of the memory cells: a) reading in atest datum; b) refreshing the test datum with a predetermined frequency;c) reading out the test datum; d) comparing the test datum that was readin with the test datum that was read out to detect whether or not thereis an error; e1) if no error was detected in step d), repeating steps a)to d) with a progressively decreased refresh frequency until the erroris detected in step d); and e2) if the error was detected in step d),repeating steps a) to d) with a progressively increased refreshfrequency until the error is not detected in step d).
 6. The methodaccording to claim 3, which comprises, during the test cycle, for eachone of the memory cells: e) reading in a test datum; f) refreshing thetest datum with a predetermined frequency; g) reading out the testdatum; h) comparing the test datum that was read in with the test datumthat was read out to detect whether or not there is an error; e1) if noerror was detected in step d), repeating steps a) to d) with aprogressively decreased refresh frequency until the error is detected instep d); and e2) if the error was detected in step d), repeating stepsa) to d) with a progressively increased refresh frequency until theerror is not detected in step d).